[9296] in cryptography@c2.net mail archive
Re: chip-level randomness?
daemon@ATHENA.MIT.EDU (Eric Rescorla)
Sat Sep 15 13:02:20 2001
To: "R. A. Hettinga" <rah@shipwright.com>
Cc: cryptography@wasabisystems.com
Reply-To: EKR <ekr@rtfm.com>
Mime-Version: 1.0 (generated by tm-edit 7.108)
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From: Eric Rescorla <ekr@rtfm.com>
Date: 14 Sep 2001 21:00:22 -0700
In-Reply-To: "R. A. Hettinga"'s message of "Fri, 14 Sep 2001 09:51:41 -0400"
Message-ID: <kj4rq53xyh.fsf@romeo.rtfm.com>
"R. A. Hettinga" <rah@shipwright.com> writes:
> I'm rooting around for stuff on hardware random number generation.
>
> More specificially, I'm looking to see if anyone has done any
> entropy-collection at the chip-architecture level as part of the logic of a
> chip.
>
> I saw somewhere the intel had done it as part of the Pentium, for instance,
> but I can't find out whether it's an actual entropy collector, or just a
> PRNG.
It's physical noise generator feeding into some postprocessing.
See: http://www.cryptography.com/intelRNG.pdf
-Ekr
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