[36043] in North American Network Operators' Group
Re: Clear Channel on a T1
daemon@ATHENA.MIT.EDU (Majdi S. Abbas)
Thu Mar 22 17:54:28 2001
Date: Thu, 22 Mar 2001 14:49:31 -0800
From: "Majdi S. Abbas" <msa@samurai.sfo.dead-dog.com>
To: Ron Buchalski <rbuchals@hotmail.com>
Cc: nanog@merit.edu
Message-ID: <20010322144931.A31454@samurai.sfo.dead-dog.com>
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In-Reply-To: <F68n4ZHkRQq5xVz5Wkm0000c578@hotmail.com>; from rbuchals@hotmail.com on Thu, Mar 22, 2001 at 10:19:35PM +0000
Errors-To: owner-nanog-outgoing@merit.edu
On Thu, Mar 22, 2001 at 10:19:35PM +0000, Ron Buchalski wrote:
> Forcing the 8th bit to a '1' isn't done to maintain timing.
Huh?
> The 8th bit was forced to a '1' to maintain ones density on the T1 line.
> Early T1 specs did not allow more than 15 consecutive zeros to be
> transmitted because the T1 repeaters along the line rely on periodic pulses
> to keep their oscillators active. It was not a problem for voice circuits,
Yes, and this was necessary to prevent those repeaters from losing
sync -- thus maintaining timing.
--msa
