[22801] in Perl-Users-Digest
Perl-Users Digest, Issue: 5022 Volume: 10
daemon@ATHENA.MIT.EDU (Perl-Users Digest)
Wed May 21 21:10:40 2003
Date: Wed, 21 May 2003 18:10:18 -0700 (PDT)
From: Perl-Users Digest <Perl-Users-Request@ruby.OCE.ORST.EDU>
To: Perl-Users@ruby.OCE.ORST.EDU (Perl-Users Digest)
Perl-Users Digest Wed, 21 May 2003 Volume: 10 Number: 5022
Today's topics:
Re: Problem with regular expression evaluation from per <nospam-abuse@ilyaz.org>
Re: Problem with regular expression evaluation from per <Samue.Irlapati@nospam.unisys.com>
Re: Problem with regular expression evaluation from per <samuel.irlapati@nospam.unisys.com>
Regexp Multiple Matching Problem (Big Brother)
Re: Regexp Multiple Matching Problem <dcutter@gmx.de>
Re: Regexp Multiple Matching Problem <michael.p.broida@boeing.com>
Re: Shutting Down Windoze (Tad McClellan)
Re: Shutting Down Windoze <abigail@abigail.nl>
trying to create spaces <chris_12003@yahoo.com>
Re: trying to create spaces <abigail@abigail.nl>
Re: trying to create spaces <bwalton@rochester.rr.com>
Re: underscoring initialisms <krahnj@acm.org>
wierd behaviour in writing out a file <TruthXayer@yahoo.com>
Re: worth a look <uri@stemsystems.com>
Digest Administrivia (Last modified: 6 Apr 01) (Perl-Users-Digest Admin)
----------------------------------------------------------------------
Date: Wed, 21 May 2003 20:58:56 +0000 (UTC)
From: Ilya Zakharevich <nospam-abuse@ilyaz.org>
Subject: Re: Problem with regular expression evaluation from perl 5.6 to 5.8
Message-Id: <bagpag$uju$1@agate.berkeley.edu>
[A complimentary Cc of this posting was sent to
Tassilo v. Parseval
<tassilo.parseval@post.rwth-aachen.de>], who wrote in article <baedvr$drf$1@nets3.rz.RWTH-Aachen.DE>:
> > in a new version of perl. I don't have a cut and pastable example, but
> > one typical case was when a `?' (meaning 0 or one occurences) had to be
> > replaced with {0,1}. Re's are particularly tricky in that the re will
> > appear to be working just fine - it's only for a particular type string
> > being matched that you'll notice a discrepancy in the matching of the two
> > versions of perl.
>
> To me that sounds a little as though the scripts for the older release
> were relying on some sort of bug or semi-bug.
One of `?' vs `{0,1}' ? At least with versions of the REx engine I
knew they culd not have been different - IIRC, were no special code to
handle `?', it was translated to {0,1}. It would be interesting to
see such a REx...
> Or, that such a new bug
> had been introduced into the new Perl release.
I do not see it (with build 19053 I have here):
perl -Ilib -Mre=debug -wle "$aa='xx'; /_${aa}$/"
Compiling REx `_xx$'
Of course, it might have been that the contents of $aa matters...
> > Another example from 5.5 => 5.6 that I remember clearly was that the
> > logic
> >
> > if (not (list) = function() ) { die }
> >
> > had to be changed to
> >
> > if (not ( (list) = function() ) ) { die }
>
> But that is really strange. I can't see how such a statement could be
> ambiguous or subject to subtle differences in the respective Perl
> interpreter.
The syntax of `not' changed. Before it was not recognized as unary
operator (it was handled by a special case in the parser); now it
behaves as a unary operator IIRC (if it looks like a function, it is a
function). So it is parsed as
( not (list) ) = function()
Treating `not SOMETHING' as an argument to grep also changed some time ago.
I found another GOTCHA for 5.8 parser - oups, cannot reproduce it with
the scant info I saved...
Ilya
------------------------------
Date: Wed, 21 May 2003 18:54:17 -0400
From: "Samuel J. Irlapati" <Samue.Irlapati@nospam.unisys.com>
Subject: Re: Problem with regular expression evaluation from perl 5.6 to 5.8
Message-Id: <bagvqv$ho4$1@trsvr.tr.unisys.com>
This is a multi-part message in MIME format.
--------------010109090001070900010205
Content-Type: text/plain; charset=us-ascii; format=flowed
Content-Transfer-Encoding: 7bit
Gregory K. Deal wrote:
> We have a regular expression that runs as expected in perl 5.6, yet
> functions differently (and thought to be wrong) in 5.8. Did RE handling
> change in 5.8, were we doing something illegal or implementation dependent,
> or what? Thanks for any input.
>
> Original statement in 5.6 :
> regular expression as an IF argument : if ($inst2_key =~
> /_${index}$/) { . . . .
> This finds the pattern specified in the $index variable at the end of
> the line. But, in 5.8, the IF did not match.
>
> Modified statement in 5.8 :
> regular expression now : if ($inst2_key =~ /_${index}/m) { . . . .
> This works as expected in 5.6 and 5.8
>
>
We tried to duplicate the error by writing a seperate script but were
unsuccesful. So I took the orignal script and stripped it down from
about 800 lines of code to 150 lines of code of which 50 lines are comments.
I am attaching all the files with this email. There are 6 files.
To test it, just execute text.sh and do a diff on temp1.vhd and temp2.vhd.
The perl script is connect_xp1.
The rest of the files are data files.
Even though we got a work-around for this, we would like others to take
a look at it since we think there maybe a perl bug lingering around.
--------------010109090001070900010205
Content-Type: text/plain;
name="connect_xp1"
Content-Transfer-Encoding: 7bit
Content-Disposition: inline;
filename="connect_xp1"
#!/usr/local/bin/perl
$top_level_e_vhd = $ARGV[0];
## If second command line argument exists, set to component list
## otherwise component list is component.list
if( exists $ARGV[1] ){
print STDERR "component list is: $ARGV[1]\n";
$comp_list = $ARGV[1];
}else {
print STDERR "component list is: component.list\n";
$comp_list = "component.list";
}
## Open component list with sub-entity vhdls
open( COMP_LIST, "$comp_list" ) || die "cannot open $comp_list";
while(<COMP_LIST>){
chomp;
@line = split;
## Store vhdl file names
$vhdl{$line[0]} = $line[0];
## Store information of number of instantiations for each vhdl
if($#line == 1 ) { $numb_inst{$line[0]} = $line[1] }
else { $numb_inst{$line[0]} = 1 }
}
close(COMP_LIST);
## Get Port information and print component statements to top level vhdl
## for each vhdl listed in component list
foreach $vhdl_key (keys %vhdl){
## Initialize to not in entity statement, and index for port number to 0
$in_entity = 0;
$port_num = 0;
## Open vhd file for current component
open (VHDL, "$vhdl_key") || die "cannot open $vhdl[$i]";
while (<VHDL>){
chomp;
## Store line as variable
$line = $_;
#Substitute spaces for special characters
$_ =~ s/(\:|\(|\)|\;|\=)/ /g;
# Store line as an array
@line = split;
## If reach end of entity, set in_entity to 0 and print end component to top
## to top level vhdl
if ($line[0] eq "end" && $in_entity == 1){
$in_entity = 0;
}
## If in entity statement, write lines to component declaration at top level
if ($in_entity == 1 && !($line[0] =~ /^--/)){
## If line is port declaration
if ($line[0] =~ /^[a-zA-Z0-9_]/ && !($line[0] =~ /^port/i) ){
## Store port info for entities instaniated more than once
for $j (0 .. $numb_inst{$vhdl_key} - 1){
## Create current instance name. Add index to the end if it is one of multiple
## instantiations
if($numb_inst{$vhdl_key} eq 1) {$curr_inst = "UQ_" . $curr_entity}
else {$curr_inst = "UQ_" . $curr_entity . "_" . $j}
## Create array that matches instance names to entity names
$inst2entity{$curr_inst} = $curr_entity;
## Store port order, direction and type
## Store vector ports seperately
if ($line[2] =~ /vector/ ) {
## Process single bit ports seperately
} else {
## Create inout, sink and source hashes with port information
if ( $line[1] eq "inout" ) {
$inout{$line[0]}[$#{ $inout{$line[0]} } + 1] = $curr_inst;
}
if ( $line[1] eq "buffer" || $line[1] eq "out" ) {
$source{$line[0]}[$#{ $source{$line[0]} } + 1] = $curr_inst;
}
if ( $line[1] eq "in" ) {
$sink{$line[0]}[$#{ $sink{$line[0]} } + 1] = $curr_inst;
}
## Port list for connection processing
$port{$line[0]}[$#{$port{$line[0]}} + 1] = $curr_inst;
## Port order for intantiation phase
$port_order{$curr_inst}[$port_num] = $line[0];
}
$type{$line[0]}{$curr_inst} = $line[2];
}
$port_num++;
}
}
##If line is entity declaration, change to component declaration
## and print to top level vhdl
if ($line[0] eq "entity"){
$_ =~ s/entity/component/;
## Set in entity condition to 1
$in_entity = 1;
## Set current entity variable
$curr_entity = $line[1];
}
}
}
close(VHDL);
## Set index for dummy signals that will be greated to connect to multiple drivers to 0
$t = 0;
## For each single bit port, run through connection process
foreach $port_key (keys %port){
## Initial to zero, will be set to 1 if the ports do not connect properly
$disconnect_check = 0;
## Check if there are no drivers
if ( $#{$source{$port_key}} == -1 && $#{$inout{$port_key}} == -1 && $#{$sink{$port_key}} >= 0 ){
$disconnect_check = 1;
## Set connection information for sinks with no drivers
for $i (0 .. $#{$sink{$port_key}}){
$connect{$port_key}{$sink{$port_key}[$i]} = "SIGNAL_gnd(0)";
$disconnect_sink{$port_key}{$sink{$port_key}[$i]} = $sink{$port_key}[$i];
$error{$port_key}{$sink{$port_key}[$i]} = "(E) Sink port with no driver";
}
}
## Check if there are no loads
if ( $#{$source{$port_key}} == 0 && $#{$inout{$port_key}} == -1 && $#{$sink{$port_key}} == -1 ){
$disconnect_check = 1;
$disconnect_source{$port_key}{$source{$port_key}[0]} = $source{$port_key}[0];
$error{$port_key}{$source{$port_key}[0]} = "(E) Source with no sinks";
}
}
## Make multiple inst. port connections for single bit source to sink/inout
## For each disconnected source port
foreach $source_key (keys %disconnect_source){
## For each instance that contains a disconnected source port
foreach $inst_key (keys %{ $disconnect_source{$source_key}}){
##Check to see if the source port ends in _ followed by a number
if($source_key =~ /_[0-9]$/){
## Create a port name by removing the number index
@sport = split(/\_/, $source_key);
$index = $sport[$#sport];
$test_port = $source_key;
$test_port =~ s/_${index}//;
## Find instances with disconnected sinks of the name test port
foreach $inst2_key (keys %{ $disconnect_sink{$test_port} }){
## If the instance name ends with the same index
if($inst2_key =~ /_${index}/m){
print "ERROR: matched end of line!\n"
} else {
print "ERROR: did not match end of line!\n"
}
}
}
}
}
--------------010109090001070900010205
Content-Type: text/plain;
name="ip_units.vhd"
Content-Transfer-Encoding: 7bit
Content-Disposition: inline;
filename="ip_units.vhd"
entity IP_UNITS is
port(
CLKBG2_IP : in std_logic ; --
CLKBG_IP : in std_logic ; -- Master clock for GRAs
CLKBT_IP : in std_logic ; -- Master clock for transparent latches.
CLKB_IP : in std_logic ; -- Master clock
CLKCG2_IP : in std_logic ; --
CLKCG_IP : in std_logic ; -- Slave clock for GRAs
CLKCR_IP : in std_logic ; --
CLKCT_IP : in std_logic ; -- Slave clock for transparent latches.
CLKC_IP : in std_logic ; -- Slave clock
CLKAB_IP : in std_logic;
CLKBB_IP : in std_logic;
CLKCB_IP : in std_logic;
CLK_ST_IP : in std_logic
);
end IP_UNITS;
--------------010109090001070900010205
Content-Type: text/plain;
name="maintenance.vhd"
Content-Transfer-Encoding: 7bit
Content-Disposition: inline;
filename="maintenance.vhd"
entity MAINTENANCE is
port (
CLKAB_IP_0 : buffer std_logic ;
CLKAB_IP_1 : buffer std_logic ;
CLKBB_IP_0 : buffer std_logic ;
CLKBB_IP_1 : buffer std_logic ;
CLKB_IP_0 : buffer std_logic ;
CLKB_IP_1 : buffer std_logic ;
CLKBG2_IP_0 : buffer std_logic ;
CLKBG2_IP_1 : buffer std_logic ;
CLKBG_IP_0 : buffer std_logic ;
CLKBG_IP_1 : buffer std_logic ;
CLKBT_IP_0 : buffer std_logic ;
CLKBT_IP_1 : buffer std_logic ;
CLKCB_IP_0 : buffer std_logic ;
CLKCB_IP_1 : buffer std_logic ;
CLKC_IP_0 : buffer std_logic ;
CLKC_IP_1 : buffer std_logic ;
CLKCG2_IP_0 : buffer std_logic ;
CLKCG2_IP_1 : buffer std_logic ;
CLKCG_IP_0 : buffer std_logic ;
CLKCG_IP_1 : buffer std_logic ;
CLKCR_IP_0 : buffer std_logic ;
CLKCR_IP_1 : buffer std_logic ;
CLKCT_IP_0 : buffer std_logic ;
CLKCT_IP_1 : buffer std_logic ;
CLK_ST_IP_0 : buffer std_logic ;
CLK_ST_IP_1 : buffer std_logic
);
end MAINTENANCE;
--------------010109090001070900010205
Content-Type: application/x-sh;
name="test.sh"
Content-Transfer-Encoding: 7bit
Content-Disposition: inline;
filename="test.sh"
cp -f zz_connect_xp1.push2 zz_connect_xp1.push3
cp -f zz_connect_xp1.push1 zz_connect_xp1.push2
cp -f connect_xp1 zz_connect_xp1.push1
cp -f connect_xp1 connect_xp2
ed connect_xp2 <<-!end
1,$ s/\/m/\$\//
w
q
!end
./connect_xp1 yagi_e.vhd yagi_component.list >| temp1.vhd
./connect_xp2 yagi_e.vhd yagi_component.list >| temp2.vhd
--------------010109090001070900010205
Content-Type: text/plain;
name="yagi_component.list"
Content-Transfer-Encoding: 7bit
Content-Disposition: inline;
filename="yagi_component.list"
ip_units.vhd 2
maintenance.vhd
--------------010109090001070900010205
Content-Type: text/plain;
name="yagi_e.vhd"
Content-Transfer-Encoding: 7bit
Content-Disposition: inline;
filename="yagi_e.vhd"
entity YAGI is
port (
VREFN_T : in std_logic
);
end YAGI;
--------------010109090001070900010205--
------------------------------
Date: Wed, 21 May 2003 19:04:06 -0400
From: Samuel Irlapati <samuel.irlapati@nospam.unisys.com>
Subject: Re: Problem with regular expression evaluation from perl 5.6 to 5.8
Message-Id: <pan.2003.05.21.23.03.58.251733@nospam.unisys.com>
On Wed, 21 May 2003 18:54:17 -0400, Samuel J. Irlapati wrote:
> Gregory K. Deal wrote:
>> We have a regular expression that runs as expected in perl 5.6, yet
>> functions differently (and thought to be wrong) in 5.8. Did RE handling
>> change in 5.8, were we doing something illegal or implementation dependent,
>> or what? Thanks for any input.
>>
>> Original statement in 5.6 :
>> regular expression as an IF argument : if ($inst2_key =~
>> /_${index}$/) { . . . .
>> This finds the pattern specified in the $index variable at the end of
>> the line. But, in 5.8, the IF did not match.
>>
>> Modified statement in 5.8 :
>> regular expression now : if ($inst2_key =~ /_${index}/m) { . . . .
>> This works as expected in 5.6 and 5.8
>>
>>
>
> We tried to duplicate the error by writing a seperate script but were
> unsuccesful. So I took the orignal script and stripped it down from
> about 800 lines of code to 150 lines of code of which 50 lines are comments.
>
> I am attaching all the files with this email. There are 6 files.
>
> To test it, just execute text.sh and do a diff on temp1.vhd and temp2.vhd.
>
> The perl script is connect_xp1.
>
> The rest of the files are data files.
>
> Even though we got a work-around for this, we would like others to take
> a look at it since we think there maybe a perl bug lingering around.
>
OK So i realized that the files got pasted and not attached. So I will
paste the files now with a begin and end header
---- Begin, file name "test.sh" -------------------
cp -f zz_connect_xp1.push2 zz_connect_xp1.push3
cp -f zz_connect_xp1.push1 zz_connect_xp1.push2
cp -f connect_xp1 zz_connect_xp1.push1
cp -f connect_xp1 connect_xp2
ed connect_xp2 <<-!end
1,$ s/\/m/\$\//
w
q
!end
./connect_xp1 yagi_e.vhd yagi_component.list >| temp1.vhd
./connect_xp2 yagi_e.vhd yagi_component.list >| temp2.vhd
---- End, file name "test.sh" -------------------
---- Begin, file name "connect_xp1" -------------------
#!/usr/local/bin/perl
$top_level_e_vhd = $ARGV[0];
## If second command line argument exists, set to component list
## otherwise component list is component.list
if( exists $ARGV[1] ){
print STDERR "component list is: $ARGV[1]\n";
$comp_list = $ARGV[1];
}else {
print STDERR "component list is: component.list\n";
$comp_list = "component.list";
}
## Open component list with sub-entity vhdls
open( COMP_LIST, "$comp_list" ) || die "cannot open $comp_list";
while(<COMP_LIST>){
chomp;
@line = split;
## Store vhdl file names
$vhdl{$line[0]} = $line[0];
## Store information of number of instantiations for each vhdl
if($#line == 1 ) { $numb_inst{$line[0]} = $line[1] }
else { $numb_inst{$line[0]} = 1 }
}
close(COMP_LIST);
## Get Port information and print component statements to top level vhdl
## for each vhdl listed in component list
foreach $vhdl_key (keys %vhdl){
## Initialize to not in entity statement, and index for port number to 0
$in_entity = 0;
$port_num = 0;
## Open vhd file for current component
open (VHDL, "$vhdl_key") || die "cannot open $vhdl[$i]";
while (<VHDL>){
chomp;
## Store line as variable
$line = $_;
#Substitute spaces for special characters
$_ =~ s/(\:|\(|\)|\;|\=)/ /g;
# Store line as an array
@line = split;
## If reach end of entity, set in_entity to 0 and print end component to top
## to top level vhdl
if ($line[0] eq "end" && $in_entity == 1){
$in_entity = 0;
}
## If in entity statement, write lines to component declaration at top level
if ($in_entity == 1 && !($line[0] =~ /^--/)){
## If line is port declaration
if ($line[0] =~ /^[a-zA-Z0-9_]/ && !($line[0] =~ /^port/i) ){
## Store port info for entities instaniated more than once
for $j (0 .. $numb_inst{$vhdl_key} - 1){
## Create current instance name. Add index to the end if it is one of multiple
## instantiations
if($numb_inst{$vhdl_key} eq 1) {$curr_inst = "UQ_" . $curr_entity}
else {$curr_inst = "UQ_" . $curr_entity . "_" . $j}
## Create array that matches instance names to entity names
$inst2entity{$curr_inst} = $curr_entity;
## Store port order, direction and type
## Store vector ports seperately
if ($line[2] =~ /vector/ ) {
## Process single bit ports seperately
} else {
## Create inout, sink and source hashes with port information
if ( $line[1] eq "inout" ) {
$inout{$line[0]}[$#{ $inout{$line[0]} } + 1] = $curr_inst;
}
if ( $line[1] eq "buffer" || $line[1] eq "out" ) {
$source{$line[0]}[$#{ $source{$line[0]} } + 1] = $curr_inst;
}
if ( $line[1] eq "in" ) {
$sink{$line[0]}[$#{ $sink{$line[0]} } + 1] = $curr_inst;
}
## Port list for connection processing
$port{$line[0]}[$#{$port{$line[0]}} + 1] = $curr_inst;
## Port order for intantiation phase
$port_order{$curr_inst}[$port_num] = $line[0];
}
$type{$line[0]}{$curr_inst} = $line[2];
}
$port_num++;
}
}
##If line is entity declaration, change to component declaration
## and print to top level vhdl
if ($line[0] eq "entity"){
$_ =~ s/entity/component/;
## Set in entity condition to 1
$in_entity = 1;
## Set current entity variable
$curr_entity = $line[1];
}
}
}
close(VHDL);
## Set index for dummy signals that will be greated to connect to multiple drivers to 0
$t = 0;
## For each single bit port, run through connection process
foreach $port_key (keys %port){
## Initial to zero, will be set to 1 if the ports do not connect properly
$disconnect_check = 0;
## Check if there are no drivers
if ( $#{$source{$port_key}} == -1 && $#{$inout{$port_key}} == -1 && $#{$sink{$port_key}} >= 0 ){
$disconnect_check = 1;
## Set connection information for sinks with no drivers
for $i (0 .. $#{$sink{$port_key}}){
$connect{$port_key}{$sink{$port_key}[$i]} = "SIGNAL_gnd(0)";
$disconnect_sink{$port_key}{$sink{$port_key}[$i]} = $sink{$port_key}[$i];
$error{$port_key}{$sink{$port_key}[$i]} = "(E) Sink port with no driver";
}
}
## Check if there are no loads
if ( $#{$source{$port_key}} == 0 && $#{$inout{$port_key}} == -1 && $#{$sink{$port_key}} == -1 ){
$disconnect_check = 1;
$disconnect_source{$port_key}{$source{$port_key}[0]} = $source{$port_key}[0];
$error{$port_key}{$source{$port_key}[0]} = "(E) Source with no sinks";
}
}
## Make multiple inst. port connections for single bit source to sink/inout
## For each disconnected source port
foreach $source_key (keys %disconnect_source){
## For each instance that contains a disconnected source port
foreach $inst_key (keys %{ $disconnect_source{$source_key}}){
##Check to see if the source port ends in _ followed by a number
if($source_key =~ /_[0-9]$/){
## Create a port name by removing the number index
@sport = split(/\_/, $source_key);
$index = $sport[$#sport];
$test_port = $source_key;
$test_port =~ s/_${index}//;
## Find instances with disconnected sinks of the name test port
foreach $inst2_key (keys %{ $disconnect_sink{$test_port} }){
## If the instance name ends with the same index
if($inst2_key =~ /_${index}/m){
print "ERROR: matched end of line!\n"
} else {
print "ERROR: did not match end of line!\n"
}
}
}
}
}
---- End, file name "connect_xp1" ---------------------
---- Begin, file name "yagi_e.vh" -------------------
entity YAGI is
port (
VREFN_T : in std_logic
);
end YAGI;
---- End, file name "yagi_e" ---------------------
--ip_units.vhd 2
maintenance.vhd-- Begin, file name "yagi_component.list" -------------------
---- End, file name "yagi_component.list" ---------------------
---- Begin, file name "maintenance.vhd" -------------------
entity MAINTENANCE is
port (
CLKAB_IP_0 : buffer std_logic ;
CLKAB_IP_1 : buffer std_logic ;
CLKBB_IP_0 : buffer std_logic ;
CLKBB_IP_1 : buffer std_logic ;
CLKB_IP_0 : buffer std_logic ;
CLKB_IP_1 : buffer std_logic ;
CLKBG2_IP_0 : buffer std_logic ;
CLKBG2_IP_1 : buffer std_logic ;
CLKBG_IP_0 : buffer std_logic ;
CLKBG_IP_1 : buffer std_logic ;
CLKBT_IP_0 : buffer std_logic ;
CLKBT_IP_1 : buffer std_logic ;
CLKCB_IP_0 : buffer std_logic ;
CLKCB_IP_1 : buffer std_logic ;
CLKC_IP_0 : buffer std_logic ;
CLKC_IP_1 : buffer std_logic ;
CLKCG2_IP_0 : buffer std_logic ;
CLKCG2_IP_1 : buffer std_logic ;
CLKCG_IP_0 : buffer std_logic ;
CLKCG_IP_1 : buffer std_logic ;
CLKCR_IP_0 : buffer std_logic ;
CLKCR_IP_1 : buffer std_logic ;
CLKCT_IP_0 : buffer std_logic ;
CLKCT_IP_1 : buffer std_logic ;
CLK_ST_IP_0 : buffer std_logic ;
CLK_ST_IP_1 : buffer std_logic
);
end MAINTENANCE;
---- End, file name "maintenance.vhd" ---------------------
---- Begin, file name "ip_units.vhd" -------------------
entity IP_UNITS is
port(
CLKBG2_IP : in std_logic ; --
CLKBG_IP : in std_logic ; -- Master clock for GRAs
CLKBT_IP : in std_logic ; -- Master clock for transparent latches.
CLKB_IP : in std_logic ; -- Master clock
CLKCG2_IP : in std_logic ; --
CLKCG_IP : in std_logic ; -- Slave clock for GRAs
CLKCR_IP : in std_logic ; --
CLKCT_IP : in std_logic ; -- Slave clock for transparent latches.
CLKC_IP : in std_logic ; -- Slave clock
CLKAB_IP : in std_logic;
CLKBB_IP : in std_logic;
CLKCB_IP : in std_logic;
CLK_ST_IP : in std_logic
);
end IP_UNITS;
---- End, file name "ip_units.vhd" ---------------------
------------------------------
Date: 21 May 2003 11:51:22 -0700
From: jonasb@alum.rpi.edu (Big Brother)
Subject: Regexp Multiple Matching Problem
Message-Id: <79c1dbe1.0305211051.687aebe6@posting.google.com>
Hi -
I am writing a script that parses through a file line by line to
search for IP addresses (it's to make syslog files available in HTML
with the IPs highlighted). I've got the code working for the first IP
on each line, but it never goes on to match if there is a second IP on
the line. So I have...
if($_=~/IPmatchingregexp/)
{
do stuff
}
I tried replacing the if with a while, but it seems to go into an
infinite loop. Can anyone help me on how do basically do a:
foreach(matched regexp)? I want to run the "do stuff" code for each IP
on the line, not just the first.
Thanks!
B
------------------------------
Date: Wed, 21 May 2003 21:33:33 +0200
From: Daniel Cutter <dcutter@gmx.de>
Subject: Re: Regexp Multiple Matching Problem
Message-Id: <bagk99$734$1@news.eusc.inter.net>
while(/IPmatchingregexp/g)
{
# do stuff
}
You'd help yourself quite a lot by reading the documentation that comes
with perl.
Daniel
> Hi -
>
> I am writing a script that parses through a file line by line to
> search for IP addresses (it's to make syslog files available in HTML
> with the IPs highlighted). I've got the code working for the first IP
> on each line, but it never goes on to match if there is a second IP on
> the line. So I have...
> if($_=~/IPmatchingregexp/)
> {
> do stuff
> }
>
> I tried replacing the if with a while, but it seems to go into an
> infinite loop. Can anyone help me on how do basically do a:
> foreach(matched regexp)? I want to run the "do stuff" code for each IP
> on the line, not just the first.
>
> Thanks!
> B
------------------------------
Date: Wed, 21 May 2003 19:43:25 GMT
From: "Michael P. Broida" <michael.p.broida@boeing.com>
Subject: Re: Regexp Multiple Matching Problem
Message-Id: <3ECBD6DD.1C211D35@boeing.com>
Big Brother wrote:
>
> Hi -
>
> I am writing a script that parses through a file line by line to
> search for IP addresses (it's to make syslog files available in HTML
> with the IPs highlighted). I've got the code working for the first IP
> on each line, but it never goes on to match if there is a second IP on
> the line. So I have...
> if($_=~/IPmatchingregexp/)
> {
> do stuff
> }
>
> I tried replacing the if with a while, but it seems to go into an
> infinite loop. Can anyone help me on how do basically do a:
> foreach(matched regexp)? I want to run the "do stuff" code for each IP
> on the line, not just the first.
Look at the docs on pattern matching with the
"g" modifier:
if (xyz =~ m/whatever/g)
Dunno where that is in perldoc, but in my edition
of the "Camel" book, it's on page 71 in a section
called "Pattern Matching Operators" talking about
the m// operator. <grin>
Basically, if you're doing the matching in list
context, it will return ALL matches at one time
as a list. If you're doing it in scalar context,
EACH time you execute that statement, it will
give you the NEXT match until it runs out.
Mike
------------------------------
Date: Wed, 21 May 2003 13:51:58 -0500
From: tadmc@augustmail.com (Tad McClellan)
Subject: Re: Shutting Down Windoze
Message-Id: <slrnbcnime.4mp.tadmc@magna.augustmail.com>
Andrew Rich <andrew.rich@bigpond.com> wrote:
> Does anyone know how to shutdown windoze ?
Please ask Windows questions in a Windows newsgroup.
--
Tad McClellan SGML consulting
tadmc@augustmail.com Perl programming
Fort Worth, Texas
------------------------------
Date: 21 May 2003 22:12:38 GMT
From: Abigail <abigail@abigail.nl>
Subject: Re: Shutting Down Windoze
Message-Id: <slrnbcnuem.kuj.abigail@alexandra.abigail.nl>
Andrew Rich (andrew.rich@bigpond.com) wrote on MMMDL September MCMXCIII
in <URL:news:pan.2003.05.21.15.17.19.898385@bigpond.com>:
)) Does anyone know how to shutdown windoze ?
With a Perl program? I've had success with:
perl -e "print qq !\t\t\b\b\b\b\b\b\b\b\b\b\b\b! while 1"
Abigail
--
perl -we 'print split /(?=(.*))/s => "Just another Perl Hacker\n";'
------------------------------
Date: Thu, 22 May 2003 00:46:03 GMT
From: "Chris" <chris_12003@yahoo.com>
Subject: trying to create spaces
Message-Id: <f5Vya.674928$OV.634214@rwcrnsc54>
nl~~nl will give me a blank line. Is there something that will give me
extra white space between characters. Right now if I type "a
b", it gets displayed as "a b".
Thanks,
Chris
------------------------------
Date: 22 May 2003 00:50:05 GMT
From: Abigail <abigail@abigail.nl>
Subject: Re: trying to create spaces
Message-Id: <slrnbco7lt.kuj.abigail@alexandra.abigail.nl>
Chris (chris_12003@yahoo.com) wrote on MMMDLI September MCMXCIII in
<URL:news:f5Vya.674928$OV.634214@rwcrnsc54>:
{} nl~~nl will give me a blank line. Is there something that will give me
{} extra white space between characters. Right now if I type "a
{} b", it gets displayed as "a b".
What on earth is your question?
Abigail
--
sub camel (^#87=i@J&&&#]u'^^s]#'#={123{#}7890t[0.9]9@+*`"'***}A&&&}n2o}00}t324i;
h[{e **###{r{+P={**{e^^^#'#i@{r'^=^{l+{#}H***i[0.9]&@a5`"':&^;&^,*&^$43##@@####;
c}^^^&&&k}&&&}#=e*****[]}'r####'`=437*{#};::'1[0.9]2@43`"'*#==[[.{{],,,1278@#@);
print+((($llama=prototype'camel')=~y|+{#}$=^*&[0-9]i@:;`"',.| |d)&&$llama."\n");
------------------------------
Date: Thu, 22 May 2003 01:01:29 GMT
From: Bob Walton <bwalton@rochester.rr.com>
Subject: Re: trying to create spaces
Message-Id: <3ECC1FDD.2000608@rochester.rr.com>
Chris wrote:
> nl~~nl will give me a blank line. Is there something that will give me
> extra white space between characters. Right now if I type "a
> b", it gets displayed as "a b".
...
> Chris
...
Well, you could try "a b". That should give you two spaces.
--
Bob Walton
------------------------------
Date: Wed, 21 May 2003 19:08:01 GMT
From: "John W. Krahn" <krahnj@acm.org>
Subject: Re: underscoring initialisms
Message-Id: <3ECBCE40.58F302F@acm.org>
Julian Day wrote:
>
> I'm looking for a regex to separate strings of letters with
> underscores in case they contain no vowels. So with the following
> where $c = consonants and $v = vowels:
>
> while (<DATA>) {
>
> s/\G($c)(?!($c)*($v))/$1_/g;
> print;
> }
>
> __DATA__
> qwrtd
> afdhgj
> shgaeklo
> dddd
>
> The output is almost what I am looking for:
>
> q_w_r_t_
> afdhgj
> shgaeklo
> d_d_d_d_
>
> Except for that nasty trailing underscore. Any alternatives? (I would
> really like to use a clean search and replace here).
$ perl -le'
@data = qw/ qwrtd afdhgj shgaeklo dddd /;
for ( @data ) {
/[aeiou]/ or $_ = join "_", split //;
print;
}
'
q_w_r_t_d
afdhgj
shgaeklo
d_d_d_d
John
--
use Perl;
program
fulfillment
------------------------------
Date: Wed, 21 May 2003 17:40:50 -0700
From: TruthXayer <TruthXayer@yahoo.com>
Subject: wierd behaviour in writing out a file
Message-Id: <3ECC1C92.E67BB860@yahoo.com>
Hi ,
Recently a relatively stable program experienced the
following problem.
It writes out a relatively large file x.out(few megs)
without any repetitive entries, just writes out
keys/values from a hash.
Now last night, it worte out the file with repetitive
entries and =
filled up the entire disk space. I suspect this is due to
some server/file system/permissions issue since I can't
replicate the problem and it behaves fine as usual.
=
o What is the cause of this wierd behaviour? How can I
prevent it in the perl script?
-- =
thanks
-Tr=DCtH
------------------------------
Date: Wed, 21 May 2003 18:26:24 GMT
From: Uri Guttman <uri@stemsystems.com>
Subject: Re: worth a look
Message-Id: <x78yt06trj.fsf@mail.sysarch.com>
and your perl question is?
ask moronzilla to help you out.
uri
--
Uri Guttman ------ uri@stemsystems.com -------- http://www.stemsystems.com
--Perl Consulting, Stem Development, Systems Architecture, Design and Coding-
Search or Offer Perl Jobs ---------------------------- http://jobs.perl.org
------------------------------
Date: 6 Apr 2001 21:33:47 GMT (Last modified)
From: Perl-Users-Request@ruby.oce.orst.edu (Perl-Users-Digest Admin)
Subject: Digest Administrivia (Last modified: 6 Apr 01)
Message-Id: <null>
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------------------------------
End of Perl-Users Digest V10 Issue 5022
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