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Special instructions for 8.4 beta on R5000 Rev. 1.x Indy

daemon@ATHENA.MIT.EDU (Robert A Basch)
Wed May 17 18:48:03 2000

Message-Id: <200005172247.SAA411889@aupair.mit.edu>
To: tlyu@MIT.EDU, jlwfnord@MIT.EDU
cc: release-team@MIT.EDU
Date: Wed, 17 May 2000 18:47:55 -0400
From: Robert A Basch <rbasch@MIT.EDU>

Hi.

You are listed as the contacts for the following machines in the
SGI beta cluster:

     capacitor-bank
     special-forces

These machines have the R5000 Revision 1.0 processor; there is a
serious bug in IRIX 6.5.7 which breaks the ability to run binaries out
of AFS on R5000 rev 1.x machines.  The bug is in kernel code which
attempts to work around a flaw in the processor.

Since Athena 8.4 (which will be in beta shortly) is based on IRIX
6.5.7, the update would fail on these machines as things stand now.
However, there is a way to disable the kernel workaround, so that AFS
binaries would run as expected.  For the beta, we are asking you to
disable the workaround manually, as described below, *before* you take
the update; we expect to have a better solution (a software fix, or a
hardware replacement) in time for the general 8.4 release.

Here are the directions for disabling the software workaround which
breaks AFS under IRIX 6.5.7 on R5000 rev 1.x Indy's:

     Bring the machine down, and enter the PROM command monitor.  At the
     ">>" prompt, enter:

         setenv -p _R5000_CVT_WAR 0

     This sets a persistent special environment variable which will disable
     the workaround in the kernel.  This is required in order for the
     update to the Athena 8.4 beta to succeed.


The processor revision can be obtained by running the IRIX command
"hinv -t cpu".

(The above setting can be undone by doing "unsetenv _R5000_CVT_WAR" at
PROM command level; this should be done after we have a fix installed
for the AFS problem under 6.5.7, since disabling the workaround leaves
the machine vulnerable to the processor flaw).


The mipscheck(1) man page contains some more information about the
problem, though it should be noted that the processor flaw actually
exists in all rev 1.x R5000's; according to the R5000 errata sheet,
the flaw was corrected in rev 2.1:

     -cvtl[:action...]
          Look for cvt.s.l and cvt.d.l instructions.  These instructions
          convert 64-bit integers to single or double floating point
          format.

     Revision [1.1] of the r5000 can misexecute cvt.s.l and cvt.d.l
     instructions when the 64-bit integer input data is in either of the
     following ranges:

          0x7FF0 0000 0000 0000    to    0x7FFF FFFF FFFF FFFF
          0x8000 0000 0000 0000    to    0x800F FFFF FFFF FFFF

     When input data is in the preceding ranges, these instructions are
     supposed to trap into the kernel where they will be emulated in
     software.  Unfortunately, they do not trap and they generate an
     incorrect result.  These instructions are fairly rare and are found in
     mips3 and mips4 executables only; they are never in mips1 or mips2
     programs.  There is a work-around for this problem, implemented
     entirely within the operating system kernel, which should be invisible
     to all user programs.  See the r5000 errata sheet for more details.

Please contact me if you have any questions about this.

Bob

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