[5523] in bugtraq
Re: Intel Pentium Bug
daemon@ATHENA.MIT.EDU (George Imburgia)
Sat Nov 8 11:16:08 1997
Date: Sat, 8 Nov 1997 00:26:38 -0500
Reply-To: George Imburgia <gti@hopi.dtcc.edu>
From: George Imburgia <gti@HOPI.DTCC.EDU>
To: BUGTRAQ@NETSPACE.ORG
In-Reply-To: <Pine.SUN.3.94.971107193930.26939A-100000@dfw.dfw.net>
From reports so far Intel Pentiums with and without MMX are vulnerable =
to
the opcode bug that locks up the cpu. Pentium Pro and Pentium II, as w=
ell
as AMD and Cyrix are not vulnerable.
Thanks to the many people who tested many platforms.
As far as the writeable microcode, mostly we have conjecture. There hav=
e
been a few press releases from Intel, and they're vague. Attached are s=
ome
of the few references.
I would hope that to write microcode, you would need custom hardware.
Intel said they are working with OEMs on this, so you might see the
feature enabled on some motherboards. A BIOS upgrade may be able to
utilize it.
Again, it's mostly conjecture... until we hear from Intel.
*If* it is accessible via rebooting for a "BIOS upgrade", it's truely
evil. It wouldn't take much to introduce predictablility into encryptio=
n,
and it's not hard to get users to reboot, they're used to windows.
begin quotes
-----------------------------------------------
Intel Studies End-User Processor Patches Intel Studies
End-User Processor Patches
by Chris Oakes
6:22pm9.Jul.97.PDT -- The ever-looming prospect of flawed CPUs, whose
designs escalate in sophistication and number of transistors with each
generation, may lead Intel to implement a way for end users to treat
hardware bugs with software fixes themselves.
"The capability already exists in the Pentium Pro and Pentium II
processors," said Intel spokesman Bill Miller. Working with Intel, OEMs
and system integrators have been using the capability to patch microcod=
e,
addressing bugs in these processors, he said. But before the company
provides a tool to end-users, it wants to study the possibilities and
potential problems surrounding such a scenario.
"The question is how do you use this capability," Miller said. "Is it
possible to take this capability and make it more broadly implementable=
?"
Possible conflicts, he said, are that a particular motherboard, BIOS, o=
r
software combination might not be receptive to a patch.
Observers confirm the existence of the chip feature, but point out that=
it
is limited in the kinds of problems it can address. Flaws like Intel's
1994 floating-point bug could not likely have been fixed with a softwar=
e
patch. "That's strictly a CPU hardware issue," said a spokesperson for
chipmaker AMD who's familiar with the technique. "That's not the kind o=
f
thing that would be fixable through [microcode]."
Martin Reynolds, vice president of technology assessment at research fi=
rm
Dataquest, agreed, saying that such a bug is beyond the scope of a
microcode fix. "Features like [microcode patches] are primarily for
debugging processes," Reynolds said. "These patches can fix some proble=
ms
easily; other problems are harder."
Because a company can't possibly test a chip's circuits completely befo=
re
manufacturing, Reynolds said, post-production fixes are achieved in two
ways. One is by altering connections with an electron microscope and th=
e
other is by making the chip's microcode programmable.
"It's not a panacea," Intel's Miller confirmed. "It's for errata - and
will not fix all errata. It's going to be one of the tools industry can
use to respond to errata." Intel defines "errata" as any case where the
performance of a processor deviates from specifications.
"What we learned in 1994 is that when we have a very open process that
involves the industry, we get all sorts of reports about the behavior o=
f
products," Miller said. In response, the company investigates these bug
"sightings" and "if it is indeed something that is errata, we then issu=
e a
write-up or publish specification updates."
Some analysts had speculated that Intel might be coming clean on a new =
or
existing flaw and might be using an announcement of this capability to
soften the impact. Miller responded, "At any time in our process we are
investigating findings that may or may not become errata. There are alw=
ays
investigations under way."
Intel is continuing to study the issue and Miller couldn't say when it
might decide on a particular course of action.
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[Intel.com Home][Contents][Search][Feedback][Support][Intel.com Home][I=
mage]
Data Integrity Features
Protecting important data and ensuring its integrity has become increas=
ingly
important as mission-critical applications continue to proliferate. To
ensure the Pentium processor's reliability, Intel ran millions of
simulations and tests. In addition, designers integrated two advanced
features traditionally associated with mainframe-class designs internal
error detection and functional redundancy testing-to help preserve data
integrity in today's evolving PC-based networks.
Internal error detection places parity bits on the internal code and da=
ta
caches, translation look aside buffers, microcode, and branch target bu=
ffer.
This feature helps detect errors in a manner that remains transparent t=
o
both the user and the system.
SL Enhanced Power Management Features
The Pentium processor family incorporates SL technology features for
superior power-management capabilities. These features operate at two
levels: the microprocessor and the system. Power management at the proc=
essor
level involves putting the processor into low power state during
non-processor intensive tasks (such as word processing), or into a very
low-power state when the computer is not in use ("sleep" mode). At the
system level, Intel's SL technology uses system management mode (SMM) t=
o
control the way power is used by the computer (including peripherals). =
This
mode provides intelligent system management that allow the microprocess=
or to
slow down, suspend, or completely shut down various system components s=
o as
to maximize energy savings. All members of the Pentium processor family
include SMM.
Multiprocessor Support
The Pentium processor is ideal for the increasing wave of multiprocessi=
ng
systems. Multiprocessing applications that combine two or more Pentium
processors are well served by the chip's advanced architecture, separat=
e
on-chip code and data caches, chip sets for controlling external caches=
, and
sophisticated data integrity features.
As previously discussed, the Pentium processor family uses the MESI pro=
tocol
to maintain cache consistency among several processors. The Pentium
processor also ensures that instructions are seen by the system in the =
order
that they were programmed. This strong ordering helps software designed=
to
run on a single-processor system to work correctly in a multiprocessing
environment.
The Pentium processor family also includes two new multiprocessor (MP)
features: a multiprocessor interrupt controller on-chip and the dual
processor mode. The processor's on-chip MP interrupt controller can sup=
port
up to 60 processors. The dual processor mode enables two processors to =
share
a single second-level cache, allowing the development of low-cost
shared-cache multiprocessor systems for workstations and low-end server=
s.
Performance Monitoring
Performance monitoring is a feature of the Pentium processor that enabl=
es
system designers and application developers to optimize their hardware =
and
software products by identifying potential code bottlenecks. Designers =
can
observe and count clocks for internal processor events that affect the
performance of data reads and writes, cache hits and misses, interrupts=
, and
bus utilization. This allows them to measure the effect that their code=
has
on both the Pentium processor architecture and their product, and to
fine-tune their application or system for optimal performance. The bene=
fit
to end users is better value and higher performance, due to the greater
synergy between the Pentium processor, its host system, and application
software.
Memory Page Size Feature
The Pentium processor offers the option of supporting either the tradit=
ional
memory page size of 4 Kbytes, or a larger 4-Mbyte page. This feature-wh=
ich
is transparent to the application software-was provided to reduce the
frequency of page swapping in complex graphics applications, frame buff=
ers,
and operating system kernels, where the increased page size allows user=
s to
map large, previously unwieldy objects. The larger page enables an incr=
eased
page hit rate, which results in higher performance.
Upgradability
As with all new implementations of the Intel 32-bit microprocessor
architecture, the Pentium processor has been designed for easy upgradab=
ility
using Intel's upgrade technology. This innovation protects user investm=
ents
by adding performance that helps to maintain the productivity levels of
Intel processor-based systems over their entire lifespans.
Upgrade technology makes it possible for users to take advantage of mor=
e
advanced processor technology in their existing systems. Intel will off=
er a
future OverDrive(R) Processor for Pentium Processors. Users should cont=
act
system manufacturers for specific systems which support upgradability.
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Legal Information =A9 1997 Intel Corporation
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