[86210] in North American Network Operators' Group

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Re: Scalability issues in the Internet routing system

daemon@ATHENA.MIT.EDU (Blaine Christian)
Wed Oct 26 14:56:42 2005

In-Reply-To: <435FC580.6020304@nrg4u.com>
Cc: nanog@nanog.org
From: Blaine Christian <blaine@blaines.net>
Date: Wed, 26 Oct 2005 14:56:22 -0400
To: Andre Oppermann <nanog-list@nrg4u.com>
Errors-To: owner-nanog@merit.edu


>
>> Another thing, it would be interesting to hear of any work on   
>> breaking the "router code" into multiple threads.  Being able to   
>> truly take advantage of multiple processors when receiving 2M  
>> updates  would be the cats pajamas.  Has anyone seen this?  I  
>> suppose MBGP  could be rather straightforward, as opposed to one  
>> big table, in a  multi-processor implementation.
>>
>
> You may want to read this thread from the beginning.  The problem  
> is not
> the routing plane or routing protocol but the forwarding plane or  
> ASIC's
> or whatever.  Both have very different scaling properties.  The  
> forwarding
> plane is at an disadvantage here because at the same time it faces  
> growth
> in table size and less time to perform a lookup .  With current  
> CPU's you
> can handle a 2M prefix DFZ quite well without killing the budget.   
> For the
> forwarding hardware this ain't the case unfortunatly.

Hi Andre...

I hear what you are saying but don't agree with the above statement.   
The problem is with the system as a whole and I believe that was the  
point Vladis, and others,  were making as well.  The forwarding plane  
is only one part of the puzzle.   How do you get the updates into the  
forwarding plane?  How do you get the updates into the router in the  
first place and how fast can you do that?   I have seen at least one  
case where the issue did not appear to be the ASICs but getting the  
information into them rapidly.  If you go and create a new ASIC  
without taking into account the manner in which you get the data into  
it you probably won't sell many routers <grin>.

BTW, I do agree that spinning new ASICs is a non-trivial task and is  
certainly the task you want to get started quickly when building a  
new system.

I did read your comment on BGP lending itself to SMP.  Can you  
elaborate on where you might have seen this?  It has been a pretty  
monolithic implementation for as long as I can remember.   In fact,  
that was why I asked the question, to see if anyone had actually  
observed a functioning multi-processor implementation of the BGP  
process.

Regards,

Blaine


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