[18287] in North American Network Operators' Group
Re: T1 Circuit actual throughput 1290Kbps
daemon@ATHENA.MIT.EDU (Robert E. Seastrom)
Thu Jul 9 11:19:13 1998
Date: Thu, 9 Jul 1998 11:05:15 -0400 (EDT)
From: "Robert E. Seastrom" <rs@bifrost.seastrom.com>
To: rs@bifrost.seastrom.com
CC: dorian@blackrose.org, ltd@interlink.com.au, tonyh@noc.cbn.net.id,
nanog@merit.edu
In-reply-to: <199807091418.KAA09952@bifrost.seastrom.com>
(rs@bifrost.seastrom.com)
From: "Robert E. Seastrom" <rs@bifrost.seastrom.com>
Precisely. The most likely explanation is that the T1 is actually D4
framed,
uh, my wrong... it's the AMI not the D4 that causes the big hit. of
course, as a matter of course, D4/AMI and ESF/B8ZS go together and you
never see combinations like D4/B8ZS... which, in answer to the fellow
who asked, is why you can't just invert the data on the HDLC and run
it down the line and get your 12% back... HDLC is layer 2, whilst
framing is layer 1...
---Rob
