[157801] in North American Network Operators' Group
Re: Whats so difficult about ISSU
daemon@ATHENA.MIT.EDU (Kasper Adel)
Thu Nov 8 20:00:52 2012
In-Reply-To: <CALBytuYh91J0RbRd374jnZJLE=LH-LVnbrRX-CTcuzP956imHg@mail.gmail.com>
Date: Fri, 9 Nov 2012 03:00:39 +0200
From: Kasper Adel <karim.adel@gmail.com>
To: Kenneth McRae <kenneth.mcrae@dreamhost.com>
Cc: NANOG list <nanog@nanog.org>
Errors-To: nanog-bounces+nanog.discuss=bloom-picayune.mit.edu@nanog.org
Does that mean they are the only vendor capable of doing this today?
I am interested in the technology behind this if this is something public,
any ideas?
Thx
On Friday, November 9, 2012, Kenneth McRae wrote:
> I have performed micro code upgrades using ISSU on the Juniper platform.
>
> On Thu, Nov 8, 2012 at 4:52 PM, Kasper Adel <karim.adel@gmail.com<javascript:_e({}, 'cvml', 'karim.adel@gmail.com');>
> > wrote:
>
>> What i was asking is full ISSU, even with micro code. I assume between
>> Major release there will be microcode upgrade most of the time.
>>
>>
>> On Fri, Nov 9, 2012 at 2:48 AM, Phil <bedard.phil@gmail.com<javascript:_e({}, 'cvml', 'bedard.phil@gmail.com');>>
>> wrote:
>>
>> > The major vendors have figured it out for the most part by moving to
>> > stateful synchronization between control plane modules and implementing
>> > non-stop routing.
>> >
>> > ALU has supported ISSU on minor releases for many years and just added
>> > support for major releases.
>> >
>> > The Cisco Nexus ISSU works well, I've done an upgrade on a 5K switch and
>> > it was completely hitless.
>> >
>> > Juniper and Cisco with the 9K have gone through some hurdles but ISSU is
>> > actually usable now if the software versions support it.
>> >
>> > The main remaining hurdle is updating microcode on linecards, they still
>> > need to be rebooted after an upgrade.
>> >
>> > Phil
>> >
>> > On Nov 8, 2012, at 6:22 PM, Kasper Adel <karim.adel@gmail.com<javascript:_e({}, 'cvml', 'karim.adel@gmail.com');>>
>> wrote:
>> >
>> > > Hello,
>> > >
>> > > We've been hearing about ISSU for so many years and i didnt hear that
>> any
>> > > vendor was able to achieve it yet.
>> > >
>> > > What is the technical reason behind that?
>> > >
>> > > If i understand correctly, the way it will be done would be simply to
>> > have
>> > > extra ASICs/HW to be able to build dual circuits accessing the same
>> > memory,
>> > > and gracefully switch from one to another. Is that right?
>> > >
>> > > Thanks,
>> > > Kim
>> >
>>
>
>
