[127751] in North American Network Operators' Group
Re: Vyatta as a BRAS
daemon@ATHENA.MIT.EDU (Christian Chapman)
Tue Jul 13 12:31:43 2010
From: "Christian Chapman" <christianchapman@eircom.net>
To: "Lamar Owen" <lowen@pari.edu>,
<nanog@nanog.org>
Date: Tue, 13 Jul 2010 23:31:25 +0700
X-SMTP2Go-MailScanner-From: christianchapman@eircom.net
Errors-To: nanog-bounces+nanog.discuss=bloom-picayune.mit.edu@nanog.org
>> Sorry, it's software running those ASIC's and FPGA's, even at that level
Sorry ..Its a clock that runs ASIC's and FPGA's
HDL is simply used to describe functionality before synthesis tools
translate the design into real hardware (gates and wires)
----- Original Message -----
From: "Lamar Owen" <lowen@pari.edu>
To: <nanog@nanog.org>
Sent: Tuesday, July 13, 2010 10:25 PM
Subject: Re: Vyatta as a BRAS
> On Tuesday, July 13, 2010 11:11:57 am Greg Whynott wrote:
>> > They are all software based, no matter who builds them. Cisco IOS,
>> > Juniper JunOS, etc.
>>
>> controlling hardware asic's and fpga's.
>
> That run low level software microcode and bitstreams. Sorry, it's
> software running those ASIC's and FPGA's, even at that level. Verilog and
> VHDL, while not your ordinary programming languages, blur the line very
> effectively.
>
