[127622] in North American Network Operators' Group
Re: Question about Manycore processor- "Tilera"
daemon@ATHENA.MIT.EDU (Valdis.Kletnieks@vt.edu)
Tue Jul 6 09:27:53 2010
To: Adrian Chadd <adrian@creative.net.au>
In-Reply-To: Your message of "Tue, 06 Jul 2010 17:09:20 +0800."
<20100706090920.GC32308@skywalker.creative.net.au>
From: Valdis.Kletnieks@vt.edu
Date: Tue, 06 Jul 2010 09:26:35 -0400
Cc: nanog@nanog.org
Errors-To: nanog-bounces+nanog.discuss=bloom-picayune.mit.edu@nanog.org
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On Tue, 06 Jul 2010 17:09:20 +0800, Adrian Chadd said:
> There's been plenty of "multi-dimensional" processor interconnects over the
> years. You should do some further research. :)
The original poster totally failed to answer the single biggest unasked
question - "What problem are you trying to solve with a Tilera?". There's
large classes of problems that will run much better on a Tilera chipset. And
there's plenty of workloads that will totally suck on that hardware.
1K cores on a chip. All hanging off one memory interconnect. I think
that about says it all right there.
> (hypercube-connected O2000, anyone?)
No thanks, I got like a half dozen of their ilk already.
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