[18975] in cryptography@c2.net mail archive
Re: solving, simplification and factorization...
daemon@ATHENA.MIT.EDU (pstach@stachliu.com)
Thu Nov 17 20:06:40 2005
X-Original-To: cryptography@metzdowd.com
X-Original-To: cryptography@metzdowd.com
Date: 17 Nov 2005 09:00:48 -0800
From: pstach@stachliu.com
To: cryptography@metzdowd.com
The answer you are looking for is Karnaugh logic maps. This will produce
an unoptimized set of gate logic that represents say S-boxes or E-tables.
>From there you can find smaller gate logic compliments that produce the
same logic map. Christopher Abad and I researched this heavily a few
years ago regarding DES S-Boxes.
He has provided his gatelogic reduction code on his site, http://www.the-mathclub.net.
I can send you my generic gate logic optimizer if you'd like. I have one
for standard (&,|,^,~), mmx/sse2 (&,|,^,~,&~), and vhdl/verilog (&,|,^,~,~&,~|,~^).
Anyhow, best of luck.
-Patrick Stach
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