[131501] in cryptography@c2.net mail archive
Re: [cryptography] 5x speedup for AES using SSE5?
daemon@ATHENA.MIT.EDU (Peter Gutmann)
Sun Aug 24 22:51:36 2008
Date: Mon, 25 Aug 2008 00:20:50 +1200
From: Peter Gutmann <pgut001@cs.auckland.ac.nz>
To: cryptography@metzdowd.com
Speaking of CPU-specific optimisations, I've seen a few algorithm proposals
from the last few years that assume that an algorithm can be scaled linearly
in the number of CPU cores, treating a multicore CPU as some kind of SIMD
engine with all cores operating in lock-step, or at least engaging in some
kind of rendezvous every couple of cycles (for example the recently-discussed
MD6 uses a round of 16 steps, if I read the description correctly) to exchange
data. This abstraction seems to be particularly convenient when dealing with
things like hash trees. However I'm not aware of any multicore CPU that
actually works this way, you'd need to have exclusive use of each core by one
thread and use incredibly expensive (compared to the other primitive CPU
operations used in hashing) barriers or something similar to ensure
synchronisation.
Is there some feature of multicore CPUs that I'm missing, or is it a case of
cryptographers abstracting a bit too much away? And if it's the latter,
should someone tell them that multicore CPUs don't actually work that way?
Peter.
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