[121694] in cryptography@c2.net mail archive
Re: "Designing and implementing malicious hardware"
daemon@ATHENA.MIT.EDU (Anne & Lynn Wheeler)
Sat Apr 26 12:03:51 2008
Date: Sat, 26 Apr 2008 11:22:06 -0400
From: Anne & Lynn Wheeler <lynn@garlic.com>
To: "Leichter, Jerry" <leichter_jerrold@emc.com>
CC: Jacob Appelbaum <jacob@appelbaum.net>,
Cryptography <cryptography@metzdowd.com>
In-Reply-To: <Pine.SOL.4.61.0804251036380.12794@mental>
Leichter, Jerry wrote:
> While analysis of the actual silicon will clearly have to be part of
> any solution, it's going to be much harder than that:
>
> 1. Critical circuitry will likely be "tamper-resistant".
> Tamper-resistance techniques make it hard to see what's
> there, too. So, paradoxically, the very mechanisms used
> to protect circuitry against one attack make it more
> vulnerable to another. What this highlights, perhaps,
> is the need for "transparent" tamper-resistance techniques,
> which prevent tampering but don't interfere with inspec-
> tion.
>
traditional approach is to make the compromise more expensive that any
reasonable expectation of benefit (security proportional to risk).
helping bracket expected fraud ROI is an infrastructure that can (quickly)
invalidate (identified) compromised units. there has been some issues
with these kinds of infrastructures since they have also been identified
with being able to support DRM (& other kinds of anti-piracy) efforts.
disclaimer: we actually have done some number of patents (that are
assigned)
in this area
http://www.garlic.com/~lynn/aadssummary.htm
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