[52221] in North American Network Operators' Group
software routers (was: Cogent service)
daemon@ATHENA.MIT.EDU (Vadim Antonov)
Sat Sep 21 06:08:13 2002
Date: Sat, 21 Sep 2002 03:06:56 -0700 (PDT)
From: Vadim Antonov <avg@exigengroup.com>
To: Stephen Sprunk <ssprunk@cisco.com>
Cc: <nanog@merit.edu>
In-Reply-To: <009b01c26115$2fe528b0$a0b58742@amer.cisco.com>
Errors-To: owner-nanog-outgoing@merit.edu
On Fri, 20 Sep 2002, Stephen Sprunk wrote:
> If you think you can make a gigabit router with PC parts, feel free.
You may be surprised to learn that BBN folks did practically that
(different CPU) with their 50 Gbps box (MGR). They had OC-48C line cards
and used Alpha 21164 CPU with pretty small 8Kb/94Kb on-chip cache to do
packet forwarding.
See C.Partridge et al in IEEE/ACM Transactions on Networking,
6(3):237-248, June 1998.
The CPUs are quite faster nowadays, and you can get things like _quad_
300MHz PPC core on an FPGA plus 20+ 3.2Gbps serdes I/Os - all on one chip.
So building multigigabit software router is a no-brainer.
(16-4-4-4-4 was in Pluris proof-of-concept; the smaller branching factor
in the radix tree was to get a better match to Pentium's L-1 cache line
size, and to make prefix insertion/deletion faster).
--vadim
PS. We were talking _mid_ 90s. Back then SSE did about 110kpps (not
advertised 250kpps) in the real life, and 166MHz Pentiums
were quite available at Fry's.
PPS. I had exactly that argument with ex-cisco hardware folks who came to
Pluris; they prevailed, and fat gobs of luck it brought them. They
ended up building a box with exactly the same fabric and comparable
mechanical and power dissipation parameters as the concept I drew as
a starting point in 98. Wasted time (and $260M) on developing these
silly ASICs when CPUs and some FPGAs could do just as nicely. I'm
glad that I wasn't around to participate in that folly.
